1. Technical Field
The present invention relates to a non-volatile storage device with electronic writing capability.
2. Related Art
A non-volatile memory is traditionally formed, for example, with a memory array of plural memory cells respectively arrayed in word lines (WL) and bit lines (BL). The bit lines of the memory cell subject to reading are sequentially connected to a read amplifier through a selection circuit, and data is read out by comparing the voltage level of the bit line connected to the memory cell by the read amplifier against a reference level.
Each of the memory cells is stored with data of “1” or “0”. The voltage level of the bit line changes according to the data stored in the memory cell subject to reading, however when, say, reading data “0” after reading data “1”, it takes some time until the bit line is charged and achieves a stable state capable of determining a 0 read, causing access delay.
As a countermeasure to address this issue there is technology described in Japanese Patent Application Laid-Open (JP-A) No. 2007-149296 that speeds up data reading by pre-charging to an internal voltage CSV generated by an internal power source when reading data from a bit line.
However, the internal voltage CSV does not always match the reference level. Accordingly, when the internal voltage CSV is higher than the reference level, as shown in FIG. 10, overshoot sometimes occurs due to the bit line being charged to a voltage exceeding the reference level by pre-charging. When the interval voltage CSV is lower than the reference level, due to the bit line being charged after pre-charging it still takes some time to achieve a stable state although this is shortened due to pre-charging.